In response to the demand for heterogeneous programming models for C/C++, and the interest in driving these models in ISO C++, the SYCL Workshop has been morphed into Distributed & Heterogeneous Programming in C/C++ to include all the programming models that have been designed to support heterogeneous programming in C and C++.
SYCL is a new Khronos specification for heterogeneous computing built on top of OpenCL and C++. The SYCL 1.2 specification was published on May 2015, and the current SYCL 2.2 specification has been published on February 2016. Behind these two specifications, there has been an important community effort ongoing for more than five years. Now with the specifications available and with Codeplay releasing their ComputeCpp Community Edition.
But many other models now exist including HPX, KoKKos, Raja, C++AMP, HCC, Boost.Compute, and CUDA to name a few. This conference aims to address the needs of both HPC and the consumer/embedded community where a number of C++ parallel programming frameworks have been developed to address the needs of multi-threaded and distributed applications. The C++11/14/17 International Standards have introduced new tools for parallel programming to the language, and the ongoing standardization effort is developing additional features which will enable support for heterogeneous and distributed parallelism into ISO C++ 20/23. This conference is an ideal place to discuss research in this domain, consolidate usage experience, and share new directions to support new hardware and memory models with the aim of passing that experience to ISO C and C++.
This workshop is based on a set of successful tutorials and workshops in different conferences, such as the SYCL tutorial at Stanford University during IWOCL and the first SYCL workshop at PPoPP’16 as well as the Berkeley Heterogeneous C++ Summit in 2016.
There is a separate workshop at SuperComputing that involves directive-based acceleration, Workshop on Accelerator Programming Using Directives (WACCPD) and one at ISC (Workshop on Performance Portable Programming Models for Accelerators) which covers many of the Performance Portability concerns of a broader set of models (P^3MA). In contrast DHPCC++ will focus on the needs of C and C++ due to the need to drive for ISO Standardization.
The 1st Distributed & Heterogeneous Programming for C/C++ (DHPCC++) Workshop will take place on the workshop track of the International Workshop on OpenCL (IWOCL 17). IWOCL 2017 will be held in Toronto, Canada, on May 16-18, 2017.
Registration for DHPCC++’17 may be completed on the the IWOCL 2017 Conference website.
Submissions: March 31, 2017 Notification: April 14, 2017 Final version: April 21, 2017 Workshop: May 16, 2017
All submissions must be made electronically through the conference submission site, at https://easychair.org/cfp/dhpcc17. Submissions may be one of the following:
- Extended abstract: Two pages in standard SIGPLAN two-column conference format (preprint mode, with page numbers)
- Short Paper: Four to six pages in standard SIGPLAN two-column conference format (preprint mode, with page numbers)
Submissions must be in PDF format and printable on US Letter size paper. All submissions will be peer-reviewed by at least two members of the program committee. We will aim to give longer presentation slots to papers than to extended abstracts. Conference papers will not be published, but made available through the website, alongside the slides used for each presentation. The aim is to enable authors to get feedback and ideas that can later go into other publications. We will encourage questions and discussions during the workshop, to create an open environment for the community to engage with.
Topics of Interest
Topics of interest include, but are not limited to:
- Future Heterogeneous programming C/C++ proposals (SYCL, Kokkos, Raja, HPX, C++AMP, Boost.Compute, CUDA …)
- ISO C/C++ related proposals and development including current related concurrency, parallelism, coroutines, executors
- C/C++ programming models for OpenCL
- Language Design Topics such as parallelism model, data model, data movement, memory layout, target platforms, static and dynamic compilation
- Applications implemented using these models including Neural Network, machine vision, HPC, CFD as well as exascale applications
- C/C++ Libraries using these models
- New proposals to any of the above specifications
- Integration of these models with other programming models
- Compilation techniques to optimize kernels using any of (clang, gcc, ..) or other compilation systems
- Performance or functional comparisons between any of these programming models
- Implementation of these models on novel architectures (FPGA, DSP, …) such as clusters, NUMA and PGAS
- Using these models in fault-tolerant systems
- Porting applications from one model to the other
- Reports on implementations
- Research on Performance Portability
- Debuggers, profilers and other tools
- Usage in a Safety security context
- Applications implemented using similar models
- Other C++ Frameworks such as Chombo, Charm++ C++ Actor Framework, UPC++ and similar
- Jakub Szuppe (Streamcomputing.eu)
- Hartmut Kaiser (Louisiana State University)
- Matthew Graham Lopez (Oak Ridge National Laboratory)
- David Alexander Beckingsdale (Lawrence Livermore National Laboratory)
- Benedict Gaster (University of the West of England)
- Michel Steuwer (Edinburgh University)
- Joel Falcou (Numscale)
- Ruyman Reyes (Codeplay Software)
- Zoltan Porkolab (Eötvös Loránd University)
- Xavier Martorell (Universitat Politècnica de Catalunya)
- Ronan Keryell (Xilinx)
- Sunita Chandrasekaran (University of Delaware)
- Bryce Lelbach (Lawrence Berkeley National Laboratory)
- Paul Keir, University of the West of Scotland (UK)
- Andrew Richards (Codeplay Software)
- Michael Wong (ISOCPP)
The reconfigurable computing community has long had the dream that software programmers will be able to use Field-Programmable Gate Arrays (FPGAs) as computing devices. With high-level synthesis (HLS) now reaching a level of quality that reasonable hardware can be generated from languages such as C, C++ and OpenCL, it would seem that having software programmers use FPGAs for computing is much closer to reality. HLS certainly overcomes a significant and important hurdle, but there are other large barriers that get very little attention for computing with FPGAs. Software programmers generally work with many abstractions, as for example with I/O to the network, and these abstractions provide important properties, such as portability and scalability. Below these abstractions, there is a significant amount of middleware infrastructure to enable and support the abstractions. Some standardization is required in the underlying platforms, particularly amongst hardware vendors, to make it easier to build, maintain and enable the infrastructure. This paper examines many issues that are often not considered when thinking about computing using FPGAs: the kinds of abstractions required, how they can be supported, what standards are needed, and the need for open standards to support an ecosystem that supports FPGAs for computing and, ultimately, an environment where software programmers can easily use FPGAs.
Dr. Paul Chow is a Professor in the Department of Electrical and Computer Engineering at the University of Toronto where he holds the Dusan and Anne Miklas Chair in Engineering Design. Prior to joining UofT in 1988 he was at the Computer Systems Laboratory at Stanford University, Stanford, CA, as a Research Associate, where he was a major contributor to an early RISC microprocessor design called MIPS-X, one of the first microprocessors with an on-chip instruction cache and the root of many concepts used in processors today. His research interests include high performance computer architectures, reconfigurable computing, embedded and application-specific processors, and field-programmable gate array architectures and applications.
|09:00||Welcome and introductions||-||Michael Wong|
|09:10||Keynote: An Open Ecosystem for Software Programmers to Compute on FPGAs||-||Dr. Paul Chow, University of Toronto, Canada|
|10:00||HiHAT: A New Way Forward for Hierarchical Heterogeneous Asynchronous Tasking||Click here||CJ|
|11:00||SYCL C++17 and OpenCL interoperability experimentation with triSYCL||-||Ronan Keryell|
|11:30||KART – A Runtime Compilation Library for Improving HPC Application Performance||-||Matthias Noack|
|12:00||Using SYCL as an Implementation Framework for HPX Compute||Click Here||Marcin Copik|
|14:00||Adding OpenCL to Eigen with SYCL||Click Here||Luke Iwanski|
|14:30||SYCL-BLAS: Leveraging Expression Trees for Linear Algebra||Click Here||Ruyman Reyes|
|15:30||Supporting Distributed and Heterogeneous Programming Models in ISO C++||-||Michael Wong|
|16:00||Towards an Asynchronous Data Flow Model for SYCL 2.2||Click Here||Ruyman Reyes|
|16:15||Towards a Unified Interface for Data Movement||Click Here||Gordon Brown|
|16:30||Channels||Click Here||Ruyman Reyes|
|16:45||Panel: What do you want in C++ for Heterogeneous||-||Ronan/Michael/Andrew/CJ|